Due to the restriction of the injection-locking mechanism, the lockable bandwidth of output signals of ordinary injection-locked frequency multiplier is small, and therefore the range of operable frequencies of the output signals thereof is limited. Please refer to FIG. 1, which illustrates an injection-locked frequency multiplier 10 according to the prior art. The injection-locked frequency multiplier 10 includes an oscillator 20 with transistors 201, 201, inductors 203, 204, and a current source 205. The injection-locked frequency multiplier 10 further includes transistors 101, 102, buffers 103, 104 and a current source 105. The buffers 103, 104 have input terminals in+, in− and output terminals out+, out−, respectively.
The oscillation frequency of the oscillator 20 is fixed, relevant to the amount of the parasitic capacitance (not shown) due to the capacitors 201, 202 and the inductors 203, 204, and to be locked at M times of basic frequency f of a differential signal SD1 by using harmonic signals SD2, SD3, which are generated by inputted the differential signal SD1 into gates G30, G40 of the transistors 101, 102, respectively. M is the ratio of injection-locked frequency multiplier. Accordingly, the range of the lockable frequency is relatively small. When there is a need to adjust the output frequency of the injection-locked frequency multiplier, not only the basic frequency f of the differential signal SD1 but also the resonated frequency of oscillator 20 which is determined by capacitances of capacitors 201, 202 and the inductances of inductors 203, 204 should be changed. Therefore, another type of injection-locked frequency multiplier is provided for improving the abovementioned deficiency.
Please refer to FIG. 2, which illustrates another injection-locked frequency multiplier by 3 times 30 according to the prior art. The injection-locked frequency multiplier 30 includes a varactor tuned and voltage controlled oscillator 301 and a harmonic generator 302. The oscillator 301 includes inductors L1, L2, capacitors C1, C2, transistors M3, M4 and a resister R1. The harmonic generator 302 includes transistors M1, M2 and a power transformer T1, which is an element disposed outer to the chip and having a primary side and a secondary side.
Referring to FIG. 2, a voltage V1 with a basic frequency f3 is applied to the primary side of the power transformer T1. When adjusting a gate bias VBIAS of the transistor M1, M2, the harmonic generator 302 can generate harmonic signals SH1, SH2 with largest gain and a frequency 3f3 being triple of the basic frequency f3. A tuning voltage VTUNE is applied to the location G to adjust the capacitances of the capacitors C1, C2, so as to increase the injection-locked range of the resonance frequency. The resistor R1 is for improving the harmonic rejection ratios. Eventually, resonance frequency signals SOSC1, SOSC2 are outputted at the drains of the transistors M3, M4, and the frequencies fOSC1, fOSC2 of the outputted signals are equal to the triple frequency 3f3.
According to the above-mentioned, it is necessary to adjust the basic frequency f3 and manually adjust the voltage VTUNE when one would like to obtain required resonance frequencies fOSC1, fOSC2, which is inconvenient. Besides, it is not easy to adjust the frequencies fOSC1, fOSC2 using the capacitors C1, C2, since the parasitic capacitance of the transistors M3, M4 are usually larger than the capacitance of the capacitors C1, C2. According, the injection-locked range of the resonance frequencies fOSC1, fOSC2 is limited. Therefore, there is a need to develop an adjustable frequency multiplier apparatus and the operating methods thereof.